This invention concerns an integrated circuit memory and particularly a register type memory in which information exists in the form of two complementary logical levels each confirming the other.
This type of memory is very sensitive to loss of information due to added energy from the outside such as, for example, the addition of energy from a heavy ion passing through the semiconductor material at the junction at which one of the two logical levels is stored.
The junction behaves like a capacitance that is charged by electron/hole pairs created during the impact with the heavy ion. If the value of the capacitance is denoted C, and the change in the charge of the capacitance resulting from the impact is denoted .DELTA.Q, there is a voltage change .DELTA.V at the capacitance terminals such that .DELTA.V=.DELTA.Q/C.
The voltage variation .DELTA.V can then reach a level such that the logical level which is stored in the junction changes, also changing the complementary logical level. The complementary logical levels confirm each other, with the result that the memory cell is in a stable state different from the initial state.
Using modern technologies, circuits can be made with smaller and smaller dimensions. The capacitance C of junctions can then be made very small. The result is that the voltage change .DELTA.V very often reaches the stored information switching limit for a low quantity of charge .DELTA.Q.
The expert in the subject knows several methods of overcoming this disadvantage.
The first method is to place a resistance R in series with each capacitance junction C, such that the time constant for each RC network thus made up is greater than the disturbance of the duration. In order to be efficient, the resistance R must be of the order of 100 to 500 k.OMEGA.. Values of this order or magnitude are difficult to achieve, particularly using the most widespread technologies at the present time in which polysilicon used to make the gates is coated with silicide. The silicide then has to be removed in order to reach the high resistance values mentioned above. This operation is difficult and gives very low efficiencies.
A second method consists of adding capacitances at sensitive nodes. The critical charge is thus increased and the voltage change .DELTA.V is reduced. In order to avoid increasing the area sensitive to disturbances, the added capacitances must not contain a diffused area. The values of capacitances are thus limited, making them less useful.
In general, these two methods have other disadvantages. Added resistances and capacitances very significantly increase the dimensions of the memory cells. Furthermore, write phases are often slowed thus reducing "set-up" and "hold" times.
This invention does not have these disadvantages.